During the semiconductor assembly process, using leadframes as chip carriers is a well-known technology. As disclosed in R.O.C. Taiwan Patent publication No. 424,313, referring to FIGS. 1 and 2, a known leadframe 10 for semiconductor chip packages comprises a plurality of leads 11, a die pad 12, and a ground ring 13. The die pad 12 is surrounded by the ground ring 13, and the leads 11 are arranged around the die pad 12 and the ground ring 13. The ground ring 13 is connected to the die pad 12 through a plurality of tie bars 14 to provide the grounding connection. In general, the ground ring 13 is adjacent to but separated from the die pad 12. At least one of the bonding wires 30 is used to connect the chip 20 and the ground ring 13. Due to the wider gaps between the die pad 12 and the ground ring 13, the position of the ground ring 13 may shift up and down during the wire bonding process, which leads to poor bonding strength.
In order to solve the problem mentioned above, another known leadframe is designed as revealed in U.S. Pat. No. 6,437,427, which comprises a plurality of inner leads, a die pad, a plurality of first tie bars, a plurality of second tie bars and a ground ring. The inner leads surround the ground ring. The ground ring is adjacent to and connected to the die pad through the first tie bars and the second tie bars. Besides, the second tie bars connect the die pad with the ground ring to avoid poor bonding strength due to wider gaps between the die pad and the ground ring during wire bonding processes. However, the effectiveness of the second tie bars to reduce the position shift of the ground ring during wire bonding processes is very limited. Moreover, the first and second tie bars are bent in order to shape a die pad with downset, the ground ring is vulnerable to twist and deform.